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Quad ISDN Echocancellation Circuit Analogue Front End Quad IEC AFE PEB 24902 Version 1.1 PEF 24902 Version 1.1
Data Sheet 5.96
T2490-211-D2-7600
PEB 24902 Revision History Previous Releases: 2.96 p. 21/22 p. 24/25 p.26 p. 28
5.96
PLL characteristics Description of ADC and table 5, ADC Fig. 10 Description of DAC
Edition 5.96 This edition was realized using the software system FrameMaker(R). Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstrae 73, 81541 Munchen
(c)
Siemens AG 1995. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
PEB 24902 PEF 24902
Table of Contents 1 1.1 1.2 1.3 1.4 1.5 2 2.1 2.2 3 3.1 3.1.1 3.1.2 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.2.5 3.2.6 3.2.7 3.2.8 3.2.9 3.3 3.3.1 3.3.2 3.3.3 3.4 3.5 4 4.1 4.2 4.3 5 5.1 5.2 6 6.1 Page
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 System Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Line Card Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 NT Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Specification of the PLL and the 15.36 MHz Master Clock (Pin CL15) . . .19 Specification of the Crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Analogue Line Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Analogue-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Range Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Digital-to-Analogue Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 External Hybrid and Transformer Parameters . . . . . . . . . . . . . . . . . . . . . .29 Analogue Loop-back Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Level Detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Power-on-Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Digital Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Frame structure on the Digital Interface in the 2B1Q Mode . . . . . . . . . . .35 Frame structure on the Digital Interface in the 4B3T mode . . . . . . . . . . . .36 Propagation Delay in transmit direction . . . . . . . . . . . . . . . . . . . . . . . . . . .37 NT-Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Boundary Scan Test Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Digital Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Static Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Dynamic Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Boundary Scan Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Supply Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Line Overload Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
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Table of Contents 7 7.1 7.2 7.3 8 Page
Environmental Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Storage and Transportation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Operating Ambient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Thermal Contact Resitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
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Overview 1 Overview
The PEB 24902 Quad IEC AFE (Quadruple ISDN Echocancellation Circuit Analogue Front End) is part of a 2B1Q or 4B3T ISDN U-transceiver chip set. Up to four lines can be accessed simultaneously by the Quad IEC AFE. The Quad IEC AFE is optimized to work in conjunction with the PEB 24901 Quad IEC DFE-T and the PEB 24911 Quad IEC DFE-Q. An integrated PLL synchronizes the 15.36 MHz Master clock onto the 8 kHz or 2048 kHz PTT Clock. This specification describes the functionality for 2B1Q and 4B3T interfaces.
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Quad ISDN Echocancellation Circuit Analogue Front End Quad IEC AFE
PEB 24902 PEF 24902
Version 1.1 1.1 * * * * * * * Features
CMOS
Digital to Analogue conversion (transmit pulse) Output buffering Analogue to digital conversion Detection of signal on the line Master clock generation by PLL P-MQFP-64 Package Compliant to ANSI T1.601 (1992), ETSI ETR 080 (1995) * JTAG boundary scan path compliant to IEEE 1149.1
P-MQFP-64-1
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Overview 1.2 Logic Symbol
Analog Line Ports
AOUT2 BOUT2 AIN2 BIN2
AOUT3 BOUT3 AIN3 BIN3
AOUT1 BOUT1 AIN1 BIN1
AOUT4 BOUT4 AIN4 BIN4
+5 V 0V
V DD d1...2, a1...4 GNDd1...2, a1...4
CODE ADDR PLLF RES
SDX SDR
Serial Interface to PEB 24901 or PEB 24911 Transmit Data from PEB 24911 in NT Mode
Mode Settings
PEB 24902
XDN1 XDN2 XDN3 XDN4 PDM1 PDM2 PDM3 PDM4
CLOCK CL15
Block Capacitors 100 nF to GND
Boundary Scan Pins
TMS TCK TDI TDO TDISS
XOUT
XIN
V REF1 V REF2 V REF3 V REF4
ADC Outputs
ITL07131
Figure 1 Logic Symbol
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Overview 1.3 Functional Block Diagram
DFE Interface
Digital Interface
D
A
Buffer Trafo Hybrid Analogue IN/OUT
Level
A
D
Voltage Reference Common PLL
D
A
Buffer Trafo Hybrid Analogue IN/OUT
Level
A
D
Voltage Reference
ITB07132
Figure 2 Block Diagram of the Quad IEC AFE
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Overview 1.4 Pin Configuration
VSS XDN3 VREF3 AIN3 BIN3 N.C. TDI TDO TCK TMS TDISS BIN4 AIN4 VREF4 XDN4 VSS
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
N.C. AOUT3 V DD N.C. BOUT3 N.C. V SS SDR PDM3 PDM2 PDM1 V DD BOUT1 N.C. V DD AOUT1
PEB 24902
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VSS XDN1 VREF1 AIN1 BIN1 ADDR CLOCK RES SDX CODE PLLF BIN2 AIN2 VREF2 XDN2 VSS
N.C. AOUT4 V DD N.C. BOUT4 V SS CL15 PDM4 XOUT XIN V DD N.C. BOUT2 N.C. V DD AOUT2
ITP07133
Figure 3 Pin Configuration (top view)
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Overview 1.5 Pin Definitions and Functions
The following tables group the pins according to their functions. They include pin name, pin number, type, a brief description of the function and cross-references referring to the sections in which the pin functions are discussed.
Table 1 Pin Definitions and Functions Pin No. Symbol Input (I) Output (O) Description Reference
Power Supply Pins 37 11 34 15 46 3 42 6 32 17 49 64 30 VDDd1 VDDd2 VDDa1 VDDa2 VDDa3 VDDa4 GNDd1 GNDd2 GNDa1 GNDa2 GNDa3 GNDa4 VREF1 I/O VREF pin to Buffer internally generated voltage with capacitor 100 nF vs. GND VREF pin to Buffer internally generated voltage with capacitor 100 nF vs. GND VREF pin to Buffer internally generated voltage with capacitor 100 nF vs. GND 2 0V analogue 5.1 0V digital 5.1 5V +/-5% analogue supply voltage 5.1 5V +/-5% digital supply voltage 5.1
19
VREF2
I/O
2
51
VREF3
I/O
2
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Overview Table 1 Pin Definitions and Functions (cont'd) Pin No. Symbol 62 VREF4 Input (I) Output (O) I/O Description VREF pin to Buffer internally generated voltage with capacitor. 100 nF vs. GND Reference 2
JTAG Boundary Scan 57 58 55 56 59 TCK TMS TDI TDO TDISS I I I O I Test Clock. Test Mode Select, internal pullup. Test Data Input, internal pullup. Test Data Output. JTAG Boundary Scan Disable, active low, internal pullup. 3.5,4.3 3.5,4.3 3.5,4.3 3.5,4.3 3.5
Line Port Pins 29 28 33 36 20 21 16 13 52 AIN1 BIN1 AOUT1 BOUT1 AIN2 BIN2 AOUT2 BOUT2 AIN3 I I O O I I O O I Differential U interface input. Line port 1 Differential U interface input. Line port 1 Differential U interface output. Line port 1 Differential U interface output. Line port 1 Differential U interface input. Line port 2 Differential U interface input. Line port 2 Differential U interface output. Line port 2 Differential U interface output. Line port 2 Differential U interface input. Line port 3 3.2.1 3.2.1 3.2.3 3.2.3 3.2.1 3.2.1 3.2.3 3.2.3 3.2.1
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Overview Table 1 Pin Definitions and Functions (cont'd) Pin No. Symbol 53 47 44 61 60 2 5 BIN3 AOUT3 BOUT3 AIN4 BIN4 AOUT4 BOUT4 Input (I) Output (O) I O O I I O O Description Differential U interface input. Line port 3 Differential U interface output. Line port 3 Differential U interface output. Line port 3 Differential U interface input. Line port 4 Differential U interface input. Line port 4 Differential U interface output. Line port 4 Differential U interface output. Line port 4 Reference 3.2.1 3.2.3 3.2.3 3.2.1 3.2.1 3.2.3 3.2.3
Digital Interface 7 CL15 I/O Master Clock 15.36 MHz. All 3.1.1, 4.2 operations and the data exchange on the digital interface are based on this clock. If a 15.36 MHz clock is generated by the internal PLL/ oscillator or if an external clock is provided at XIN then CL15 issues this clock. If the pin XIN is clamped to low or high then CL15 is input and an other device has to provide the 15.36 MHz clock. Pulse density modulated output of the 3.2.1, 4.2 second-order sigma-delta ADC of line port 1 Pulse density modulated output of the 3.2.1, 4.2 second-order sigma-delta ADC of line port 2
38
PDM1
O
39
PDM2
O
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Overview Table 1 Pin Definitions and Functions (cont'd) Pin No. Symbol 40 PDM3 Input (I) Output (O) O Description Reference
Pulse density modulated output of the 3.2.1, 4.2 second-order sigma-delta ADC of line port 3 Pulse density modulated output of the 3.2.1, 4.2 second-order sigma-delta ADC of line port 4. Input for Transmit data in NT mode. Not used in LT-Mode. Internal pulldown. Input for Transmit data in NT mode. Not used in LT-Mode. Internal pulldown. Input for Transmit data in NT mode. Not used in LT-Mode. Internal pulldown. Input for Transmit data in NT mode. Not used in LT-Mode. Internal pulldown. Interface for the transmit and control data. Up to eight lines can be multiplexed on SDX. Transmission and sampling is based on clock CL15 (15,36 MBit/sec): For each line port the following bits are exchanged: TD0, TD1, TD2: Transmit data RANGE: Range select LOOP: Analogue loop back switch PDOW: Power down/power up NT: NT-Mode or LT-Mode Synchronization information Level information for the detection of the awake tone. The four lines are multiplexed on SDR. 3.4
8
PDM4
O
31
XDN1
I
18
XDN2
I
3.4
50
XDN3
I
3.4
63
XDN4
I
3.4
24
SDX
I
3.3, 4.2
41
SDR
O
3.3, 4.2
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Overview Table 1 Pin Definitions and Functions (cont'd) Pin No. Symbol 27 23 25 ADDR CODE RES Input (I) Output (O) I I I Description Select the assignment of time slots and line ports. Select 2B1Q or 4B3T code. Code = low sets 2B1Q Code. Reset and power down of the entire IEC Quad AFE including PLL and all four line ports. Asynchronous signal, active low. Reference 3.3 3.3, 3.2.3 3.2.9
PLL 9 10 XOUT XIN O I Crystal out. 15.36 MHz crystal is connected. Leave open if not used. 3.1.2
3.1, 3.1.2 Crystal in. External 15.36 MHz clock signal or 15.36 MHz crystal is connected. Clamping XIN to either low or high sets CL15 to Input. 8 kHz or 2048 kHz clock as a time 3.1 base of the 15.36 MHz clock.Connect to GND if not used. Select corner frequency of PLL Jitter Transfer function. Internal pullup resistor. 3.1
26
CLOCK
I
22
PLLF
I
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System Integration 2 System Integration
The Quad IEC AFE is optimized for line modules in the central office or access networks (LT function) together with the PEB 24901 Quad IEC DFE-T for 4B3T code or the PEB 24911 Quad IEC DFE-Q for 2B1Q code. Application in the multi channel NT function together with the PEB 24911 Quad IEC DFE-Q V2.1 is supported. The PEB 24911 Quad IEC DFE-Q is footprint compatible to the PEB 24901 Quad IEC DFE-T. This way, one board layout can be used for both line codes simply by putting the appropriate DFE. 2.1 Line Card Application
The Quad IEC AFE is controlled via the signal at pin SDX. The transmit data is transferred the same way. Data on SDX is organized such that two Quad IEC AFE devices can share the same signal. The Quad IEC AFE can transmit either 2B1Q-data or 4B3T-data. Setting the pin CODE to low will result in 2B1Q code. For 4B3T code the pin CODE has to be tied to VDD. Each of the four line ports is biased by a separate voltage reference. This internal reference voltage has to be decoupled by a capacitor of 100 nF connected to the VREFx pin and GND. The 15.36 MHz master clock is generated with a crystal oscillator and synchronized onto the PTT clock with an integrated PLL. Fig. 4 shows a 4 channel LT application for 2B1Q line code. Note, that the PEB 24911 Quad IEC DFE-Q is footprint compatible to the PEB 24901 Quad IEC DFE-T. This way, one board layout can be used for both linecodes simply by putting the appropriate DFE.
Figure 4 4 channel LT application
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System Integration An 8 channel LT is built with two AFE/DFE sets. One Quad IEC AFE generates the master clock for all four devices. The PLL in the other Quad IEC AFE is passive.
Figure 5 8 channel LT application Figure 6 gives an overview of an 8 channel linecard.
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System Integration
Figure 6 8 channel LT application (overview)
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System Integration 2.2 NT Application
The NT-Mode is supported together with the Quad IEC DFE-Q V2.1. In this application the serial interface SDX does only carry control information. The transmit data is transferred from the Quad IEC DFE-Q V2.1 to the Quad IEC AFE asynchronously on all four ports via the pins XDN1..4. The PLL of the Quad IEC AFE is used to synchronize the crystal frequency onto the received signal of the U-interfaces. Operation of all four ports is synchronized individually onto the receive signal from the line by a digital PLL in the Quad IEC DFE-Q.
Figure 7 4 channel NT application
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Technical Description 3 3.1 Technical Description Clock Generation
All timing signals are derived from a 15.36 MHz system clock. The 15.36 MHz clock can be provided by the Quad IEC AFE by a crystal-based PLL, which is synchronized to either an 8 kHz or a 2048 kHz clock at pin CLOCK. The frequency at pin CLOCK is detected automatically. The 15.36 MHz clock can also be provided externally at pin CL15 without making use of the internal PLL. In this mode the pin XIN must be tied to either VDD or GND. An internal power-on-reset circuitry assures that the pin CL15 is an input until a 15.36 MHz clock is detected at the output of the PLL/oscillator. 3.1.1 Specification of the PLL and the 15.36 MHz Master Clock (Pin CL15)
The PLL is based on a crystal connected to the pins XIN and XOUT. For synchronization of the 15.36 MHz clock up to 16 internal capacitances are connected to XIN and XOUT. The loop filter of the PLL is of second order, therefore a sinusoidal input jitter with the angular frequency = 2f at CLOCK is amplified by the PLL according to the following formula:
2 ----- j + 1 r H ( j ) = ----------------------------------------j 2 2 ----- + ----- j + 1 r r
H(j) is the complex jitter transfer factor r = 2fr is the angular resonance-frequency of the PLL is the damping factor of the PLL The maximum phase difference between the external CLOCK and the internal reference, derived from the master clock, due to a sinusoidal input jitter with the angular frequency is given as 1 - H(j). The magnitude of the jitter transfer function and of the phase difference are illustrated below:
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Technical Description
10 10
0
H1 j H1max
10
20
30
40 40 0.01 0.01 0.1 1 f j fn 10 100 1000 1000
Figure 8 Jitter Transfer Gain in dB
20 20
0
20 H1e j 40
60
80 80 0.01 0.01 0.1 1 f j fn 10 100 1000 1000
Figure 9 Maximum Phase Difference Due to Sinusoidal Input Jitter If the input signal at pin CLOCK disappears being stuck to high or low, the PLL continues to generate the CL15 clock. In this case the PLL keeps the last setting. The accuracy of the frequency of CL15 degenerates in the long term only due to changes in temperature and ageing.
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Technical Description The resonance frequency can be set to two different values using the pin PLLF. PLLF tied to low sets the PLL to a low resonance frequency suited for applications in the Access Network. PLLF tied to high or left open results in a higher resonance frequency for accelerated synchronization. The PLLF pin has an internal pull-up resistor. The PLL automatically determines whether the frequency at pin CLOCK is 8 kHz or 2048 kHz . Table 2 PLL Characteristcs Parameter min. fr resonance frequency, PLLF = low fr resonance frequency, PLLF = high Damping factor Hmax maximum jitter amplification Synchronization time of the PLL after power on and applying the reference at pin CLOCK, PLLF = low Synchronization time of the PLL after power on and applying the reference at pin CLOCK, PLLF = high Output Jitter at CL15 without any jitter in the CLOCK signal (peak-to-peak); jitter frequency > 800 Hz Output Jitter at CL15 with-out any jitter in the CLOCK signal (peak-to-peak) jitter frequency < 20 Hz Initial accuracy after the loss of the reference clock at CLOCK Initial accuracy after power on -50 1.2 7 0.7 0.9 Limit Values typ. 1.5 8 0.9 1.45 max. 1.8 9 1.2 2.2 8 dB sec Hz Hz Unit
1
sec
2
ns
80
ns
0.5 50
ppm ppm
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Technical Description Table 2 PLL Characteristcs (cont'd) Parameter min. Start-up time of the Oscillator with the crystal suggested below. Input capacitance at XIN and XOUT Output current at XOUT during start-up Output current at XOUT after synchronization Table 3 PLL Input Requirements Parameter min. Accuracy of the reference at CLOCK to enable synchronization Peak-to peak Jitter of the CLOCK signal during any 125 sec period 3.3 Peak-to-peak voltage of a sinusoidal external master clock provided at XIN Low time of the reference at CLOCK High time of the reference at CLOCK Pulse width of the 15MHz clock 3.1.2 130 130 26 39 -150 Limit Values typ. 0 max. +150 ppm Unit 3 0.5 0.5 Limit Values typ. 0.5 max. 1 ms Unit
15 1 1
pF mA mA
70
ns
Vpp
ns ns ns
Specification of the Crystal
A crystal (serial resonance) has to be connected to XIN and XOUT which shall meet the following specification:
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Technical Description Table 4 Specification of the crystal Parameter Nominal frequency Total frequency range Operating frequency CLoad = 15 pF CLoad = 7 pF Current Load capacitance Overall tolerance f/f Resonance resistance Rr Shunt capacitance C0 Motional capacitance C1 Overall Pullability 25 +- 210 20 7 9.8 -150 15.35770 1 Min Typ 15.360000 +150 15.36230 2 10.2 60 Max Units MHz ppm MHz MHz mA pF ppm Ohm pF fF ppm
Note that the load capacitors are integrated in the PEB 24902. No additional capacitance has to be connected neither to XIN nor to XOUT. The crystal specifications shall meet the requirements given in table 4. A suitable type of crystal would be: Vibrator: Mode of vibration Crystal cut 3.2 Analogue Line Port DS ATI fundamental
The Quad IEC AFE Chip gives access to four line ports. The signal to be transmitted is issued differentially at pins AOUT1..4 and BOUT1..4. The input is differentially sampled at AIN1..4 and BIN1..4. Each line port consists of three main function blocks: - the analogue-to-digital converter in the receive path - the digital-to-analogue converter in the transmit path - the output buffer in the transmit path Furthermore a line port contains some special functions. These are: - analogue test loop-back - level detect function
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PEB 24902 PEF 24902
Technical Description 3.2.1 Analogue-to-Digital Converter
A first order low pass anti alias filter is provided at the input of the ADC. The ADC is a sigma-delta modulator of second order using a clock rate of 15.36 MHz. During normal operation the ADC evaluates the signal at AINx and BINx. The ADC evaluates the signal at AOUTx and BOUTx while the analogue loop-back is activated. The maximum peak input voltage between AINx and BINx is defined as the minimum input voltage that results in a continuous series of high or low at the PDMx pin. A larger input signal will be clipped. An increasing positive voltage at AINx - BINx will result in an increasing number of high states at the PDMx pin. Hence, the maximum positive voltage at AINx - BINx results in a series of high whereas the maximum negative voltage results in a series of low. The average percentage of high states obtained with a given input voltage is referred to as gain of the ADC. It is expressed in %/Volt. The ADC offset is the difference in % from the ideal 50 % high states with no input signal, transferred back to the input voltage using the ADC gain. The maximum signal to noise ratio is achieved by signals of approximately 65% of the maximum peak input signal voltage. The signal to noise ratio is evaluated with a digital third order low pass filter applied to the digital data stream. The filter transfer function zeroes are at 80 kHz, 80 kHz and 160 kHz. Table 5 Specified Data of the Analogue-to-Digital Converter Parameter Signal/Noise (sine wave 1.5 Vpp between AINx/BINx) Signal/(Noise+ Distortion) (sine wave 0.4 Vpp between AINx/BINx) Signal/(Noise+Distortion) (sine wave 1.5 Vpp between AINx/BINx) Signal/(Noise+Distortion) (sine wave 2.0 Vpp between AINx/BINx) 70 Limit Values min. typ. 72 max. dB range function deactivated, all line ports sending random 2B1Q pattern into 98 load range function deactivated, all line ports sending random 2B1Q pattern into 98 load range function deactivated range function deactivated range function activated Unit Test Condition
59.5
61.5
dB
65
68
dB
60
dB
Signal/(Noise + Distortion) 60 (sine wave 3 Vpp between AINx/ BINx)
Semiconductor Group 24
dB
05.96
PEB 24902 PEF 24902
Technical Description Table 5 Specified Data of the Analogue-to-Digital Converter (cont'd) Parameter Signal/Noise 65 (sine wave 3 Vpp between AINx/ BINx) Signal/(Noise + Distortion) 50 (sine wave 4 Vpp between AINx/ BINx) Signal/(Noise+Distortion) (sine wave 4.6 Vpp between AINx/BINx) DC offset voltage DC offset voltage ADC gain ADC gain 28 14 33 16.5 6 35 Limit Values min. typ. 68 max. dB range function activated, all line ports sending random 2B1Q pattern into 98 load range function activated range function activated range function deactivated range function activated Unit Test Condition
dB
dB
35 70 38 19 6.25
mV mV
%/V range function deactivated %/V range function activated dB k
Attenuation of the range function 5.75 Impedance between AINx and BINx Input capacitance at AINx and BINx Input voltage range at AINx and BINx Common Mode Rejection Ratio Power Supply Rejection Ratio Power Supply Rejection Ratio Anti Alias Filter Corner Frequency GND 40 40 55 1.1 100
3 VDD
pF
dB dB dB 1.6 2.3 MHz
f < 80 kHz f < 80 kHz 80 kHz < f < 20 MHz
Semiconductor Group
25
05.96
PEB 24902 PEF 24902
Technical Description 3.2.2 Range Function
In case the signal input is too high (low attenuation on short loops), the range function can be activated. The range function attenuates the received signal internally by 6 dB. The range function is activated by setting the RANGE bit on SDX to ONE. 3.2.3 Digital-to-Analogue Converter
The output pulse is shaped by a special DAC. The DAC is optimized for excellent matching between positive and negative pulses and high linearity. It uses a fully differential switched capacitor approach. The staircase-like output signal of the DAC drives the output buffers. The shape of a DAC output signal is shown below, the peak amplitude is normalized to one. This signal is fed to an RC low pass of first order.
Figure 10 DAC Output for a Single Pulse The duration of each pulse is 24 steps, with t = 0.78 sec per step for 2B1Q code and 0.52 sec per step for 4B3T code. The pulse rate is one pulse per 16 steps, e.g. 80 kHz for 2B1Q code and 120 kHz for 4B3T code. Thus, the subsequent pulses are overlapping for a duration of 8 steps. The output stage consists of two identical buffers, operated in a differential mode. The buffers are optimized for: - high output swing - high linearity - low quiescent current to minimize power consumption The pulse mask for a single +3 2B1Q-pulse measured between AOUTx and BOUTx at a load of 98 is given in figure 11:
Semiconductor Group
26
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PEB 24902 PEF 24902
Technical Description
Figure 11 Pulse Mask for a Single +3 Pulse (not to scale) The pulse mask for a +1 pulse is obtained by dividing all voltages in figure 11 by 3. Negative pulses are described by the corresponding negative voltages. The pulse as given in figure 11 is passing a sample and hold circuit and a first order RC low pass filter. The sample period is 0.78 s (2B1Q code) or 0.52 s (4B3T code). The switch is closed during 1/3 of the sample period. Hence, during 2 / 3 of the time, the output signal does not change. This way, a settling behavior is achieved which is slowed down by a factor of three compared to the cut-off frequency of the RC low pass filter.
Figure 12
Semiconductor Group
27
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PEB 24902 PEF 24902
Technical Description Output Pulse Sample and Hold with Filter
The relative amplitudes of the single steps of the pulse are given below. Step numbers are as referred to in figure 10. period after step no. relative level 0 1 2 3 4 5 6 7 8
0
0.0625 0.1875 0.3125 0.4375 0.5625 0.6875 0.8125 0.9375
Steps 9 to 16 have a level of 1.0. The descending steps are defined as follows: period after step no. relative level 17 18 19 20 21 22 23 24 25
0.9375 0.8125 0.6875 0.5625 0.4375 0.3125 0.1875 0.0625
0
Static tolerances of the step sizes are such that the pulse mask as given in figure 11 is provided. Dynamic tolerances are such that the nonlinearity values as given in table 6 are reached. Table 6 Specified Data of the Digital-to-Analogue-Converter Parameter min. absolute peak voltage measured 3.1 for a single +3 or -3 pulse between AOUTx and BOUTx absolute peak voltage measured 1.033 for a single +1 or -1 pulse between AOUTx and BOUTx Common mode DC level Offset between AOUTx and BOUTx ratio between 1 and 3 symbols Variation of the signal amplitude measured over a period of 1 min.
Semiconductor Group 28
Limit Values typ. 3.2 max. 3.3
Unit Test Condition V 98 load between AOUTx and BOUTx 98 load between AOUTx and BOUTx
1.067
1.1
V
2.05 - 35.5 0.3283
2.375
2.6 35.5
V mV
0.3333
0.3383 1 %
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PEB 24902 PEF 24902
Technical Description Table 6 Specified Data of the Digital-to-Analogue-Converter (cont'd) Parameter min. Peak-to-peak output jitter measured with a high-pass filter of 30 Hz cut-off frequency Peak-to-peak output jitter measured without the high-pass filter Signal / (Noise + Distortion) driving 98 in series with 6.8 V DC Signal / (Noise + Distortion) driving 98 in series with 3.2 V DC Signal / (Noise + Distortion) driving 98 in series with 0.5 V DC 26 Limit Values typ. max. 1.3 nsec jitter free 15.36 MHz clock nsec Unit Test Condition
6.5
dB
53
dB
63
68
dB
Corner frequency of the DAC RC 420 low pass filter Output Impedance AOUTx/ BOUTx 1
620 2 6
900 4 12
kHz Power-Up Power-Down
The signal to noise plus distortion ratio is measured using an evenly distributed but otherwise random sequence of +3, +1, -1, -3 (2B1Q code) or +1, 0, -1 (4B3T code) driving 98 in series with a DC voltage. The output signal at AOUT and BOUT has to be weighted with a low pass filter from 0 to 80 kHz (2B1Q code) or 120 kHz (4B3T code), respectively, to get the specified sum of noise and total harmonic distortion as given in table 6. Any linear mismatch between 3 and 1 symbols is cancelled for the S/N measurements. 3.2.4 External Hybrid and Transformer Parameters
For the 2B1Q-code and the 4B3T-code different external hybrids are suggested in figures 13 and 14. These hybrids will work correctly with an according transformer as described in table 7. Please note that table 7 gives typical transformer parameters and is not intended to be a complete transformer description. Transformer linearity must be such that no significant destortion is added to the signal passing the echo path from AOUT/BOUT to AIN/BIN.
Semiconductor Group 29 05.96
PEB 24902 PEF 24902
Technical Description
Figure 13 Example of External Hybrid Circuit for 2B1Q Code
Figure 14 Example of External Hybrid Circuit for 4B3T Code
Semiconductor Group 30 05.96
PEB 24902 PEF 24902
Technical Description Table 7 Transformer Parameters Parameter Transformation ratio; Device side : Line side Main inductance of windings on the line side Leakage inductance of windings on the line side Coupling capacitance between the windings on the device side and the windings on the line side DC resistance of the windings on device side DC resistance of the windings on line side Symbol n LH LS CK 2B1Q 1:1.6 14.5 90 100 4B3T 1:1.32 7.9 50 75 mH H pF Unit
RCu, B RCu, L
2.8 2.7
1.9 1.3

3.2.5
Analogue Loop-back Function
The loop-back bit (LOOP) set to ONE on SDX activates an internal analogue loop-back. This loop-back is closed near the U interface. Signals received on AINx / BINx will neither be evaluated nor recognized by the ADC. The output signal is attenuated by 17 dB and fed to the inputs of the ADC and level detect circuit instead. It is still available at AOUTx / BOUTx. Figure 15 shows a schematic of the loop-back function.
Semiconductor Group
31
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PEB 24902 PEF 24902
Technical Description
Figure 15 Block Diagram of Special Functions in the Quad IEC AFE 3.2.6 Level Detect
The level detect circuit evaluates the differential signal between AINx and BINx. Level detect is not affected by the range setting nor by the analog loop-back. It is also active during power down. The level detection is preceded by a first order low pass filter. The detected level is communicated to the Quad IEC DFE on SDR. The detected level is updated every 12.5 sec (2B1Q) or every 8.33 sec (4B3T). If the input signal exceeds the threshold once during this time, the level bit is set to ONE, otherwise it is set to ZERO. The level bit is repeated on SDR during the whole time slot associated with the corresponding line port. Table 8 Specified Data of the Level Detection Circuit Parameter Cut-off frequency of the input filter Threshold of level detect (2B1Q) 90 4 Limit Values min. typ. 160 max. 230 20 KHz mV Unit
Semiconductor Group
32
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PEB 24902 PEF 24902
Technical Description Table 8 Specified Data of the Level Detection Circuit Parameter Threshold of level detect (4B3T) DC level of level detect (common mode level) 10 0 Limit Values min. typ. max. 30 3 mV V Unit
3.2.7
Power down
Transmit path, receive path and auxiliary functions of the analog line port are switched to a low power consuming mode when the power down function is activated. This implies the following: - The ADC, the relevant pin PDMx is tied to GND. - The DAC and the output buffer; the pins AOUTx BOUTx are tied to GND. - The internal DC voltage reference is switched off. The VREFx pin stays at approximately 2.5 V - The range and the loop functions are deactivated. The digital interface, the PLL, and the level detection are not affected by the powerdown. 3.2.8 Power-on-Reset
When applying power to the Quad IEC AFE an internal power-on-reset is generated to reset the PLL/oscillator and to set CL15 to an input. CL15 remains an input until a clock signal is detected in the oscillator. As long as no 15.36 MHz master clock is detected the PLL control functions are switched off. 3.2.9 Reset
The reset is activated by setting pin RES to low. The following functions are reset: - The reset activates the powerdown of all line ports. - The synchronization of the digital interface is initialized. - The data on SDX is ignored during reset. - SDR is set to low - The range and the loop functions of all line ports are deactivated - The PLL is reset to it's nominal frequency and starts to resynchronize after 130 ns. All settings are maintained until RES is high and the digital interface is synchronized. 3.3 Digital Interface
On the digital interface transmit and receive data is exchanged as well as control information for the start-up procedure. The ADC output is transferred to the Quad IEC
Semiconductor Group 33 05.96
PEB 24902 PEF 24902
Technical Description DFE T or Quad IEC DFE Q on the signals PDM1..PDM4. The timing of all signals in 2B1Q mode as well as 4B3T mode is based on the 15.36 MHz clock which is provided by the Quad IEC AFE. The transmit data, powerup/down, range function and loopback are transferred on SDX, and the level status on SDR for all line ports. Eight time slots contain the data for up to eight line ports. Therefore two Quad IEC AFEs can share a single SDX signal. The slot selection pin ADDR determines the assignment of the time slots to the line ports. The allocation of these time slots is done by the ninth time slot, a 24 bit synch. word on SDX, that consists of all ZEROs. The other time slots with transmission data start with a ONE. Therefore the first ONE after at least 24 subsequent ZEROs must be the first bit of time slot no. 0. This information is also used to determine the status of synchronization of the digital interface after reset. Table 9 Assignments of Time-Slots on SDX/SDR to Line Ports Time-Slot No. (ADDR low) 0 2 4 6 Time-Slot No. (ADDR High) 1 3 5 7 Line Port No. 1 2 3 4
The code independent data on SDX: NOP: The no-operation-bit is set to ZERO if none of the control bits (PDOW, RANGE and LOOP) shall be changed. The values of the control bits of the assigned line port is latched. The states of the control bits on SDX are ignored, they should be set to ZERO to reduce any digital cross-talk to the analog signals. The NOPQ bit is set to ONE if at least one of the control bits shall be changed. In this case all control bits are transmitted with their current values. PDOW: If the PDOW bit is set to ONE, the assigned line port is switched to powerdown. Otherwise it is switched to powerup.
RANGE: RANGE = ONE activates the range function, otherwise the range function is deactivated. "Range function activated" refers to high input levels. LOOP: SY: LOOP = ONE activates the loop function, i.e. the loop is closed. Otherwise the line port is in normal operation. First bit of the time slots with transmission data. For synchronization and bit allocation on SDX and SDR, SY is set to ONE.
Semiconductor Group
34
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PEB 24902 PEF 24902
Technical Description "0": reserved bit. Reserved bits are currently not defined and shall be set to ZERO. Some of these bits may be used for test purposes or can be assigned a function in later versions. Frame structure on the Digital Interface in the 2B1Q Mode
3.3.1
The 192 available bits during a 80 kHz period (related to the 15.36 MHz clock) are divided into the 9 slots of which 8 slots are 21 bits long used for data transmission. The status on SDR is synchronized to SDX. Each time slot on SDR carries the corresponding LD bit during the last 20 bits of the slot.
Figure 16 Frame Structure on SDX and SDR in 2B1Q Mode The 2B1Q data is coded with the bits TD2, TD1, TD0: Table 10 Coding of the 2B1Q data (AOUT/BOUT) 2B1Q Data 0 -3 -1 +3 +1 TD2 1" 0 0 0 0 TD1 dont care" 0 0 1 1 TD0 dont care" 0 1 0 1
The NT-mode is set if the NT-bit on all four slots is 1". LT-mode then is only set again with a low on pin RES. If the NT-Mode is set, the TD2, TD1 and TD0 bits on SDX are don't care". The transmit data enters the device as a 80 kHz clock that determines the transmit clock. The data itself is coded onto this clock via the pulse width.
Semiconductor Group
35
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PEB 24902 PEF 24902
Technical Description 3.3.2 Frame structure on the Digital Interface in the 4B3T mode
The 128 available bits during a 120 kHz period (related to the 15.36 MHz clock) are divided into 9 slots of which 8 slots are 13 bits long used for data transmission. The status on SDR is synchronized to SDX. Each time slot on SDR carries the corresponding LD bit during the last 12 bits of the slot.
Figure 17 Frame Structure on SDX/SDR in 4B3T Mode The 4B3T data is coded with the bits TD1, TD0: Table 11 Coding of the 4B3T data pulse (AOUT/BOUT) 4B3T Data Pulse 0 +1 -1 TD1 0 1 1 TD0 0 0 1
Semiconductor Group
36
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PEB 24902 PEF 24902
Technical Description 3.3.3 Propagation Delay in transmit direction The start of the transmit pulse is defined as given in fig.18:
Figure 18 Definition of Transmit Pulse Start The delay in transmit direction depends on the slot x on SDX. The pulses on the four lines are equally spaced in time while the transmit bits on SDX are not. The delay is defined as the time from the end of last bit of the slot x on SDX until the start of the pulse at AOUT/BOUT as given in figure 18. The delay is (3x + 27) 65 ns.
*
3.4
NT-Mode Operation
The NT-Mode is provided in conjunction with the PEB 24911 Quad IEC DFE-Q V2.1. It is set by the Quad IEC DFE-Q via the NT-bit on the serial interface (see fig. 16). Note that there is no NT bit defined for the 4B3T case as the PEB 24901 Quad IEC DFE-T does not support the NT-Mode. If the NT-bit is set to 1", the bits TD2, TD1, and TD0 on SDX are not taken into account. The transmit clock is not generated from the frame on SDX. The transmit data and transmit clock are passed to the Quad IEC AFE via the XDNi pins (i = 1..4 being the port no.) as follows: The transmit clock is fed in at XDNi individually for each line port. The average period of the transmit clock is 12.5 s, which equals 192 15.36 MHz periods. In order to synchronize the upstream data to the receive data stream, the transmit clock period may be shorter or longer than 192 15.36 MHz periods. The start time of the transmit pulse is not fixed as in the LT mode. It is individually tied to the transmit signal of the different line ports. The begin of the transmit pulse at AOUT/BOUT is 50 15.36 MHz periods = 3.26s after the rising edge of the signal at XDNi. The data is coded via the pulse width onto the transmit clock:
Semiconductor Group
37
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PEB 24902 PEF 24902
Technical Description Table 12 Coding of the 2B1Q data (AOUT/BOUT) in the NT-mode 2B1Q Data 0 -3 -1 +3 +1 high time (no. of 15.36 MHz periods 37 5 13 21 29
Figure 19 Coding of the Transmit Signal in NT-Mode (not to scale)
Semiconductor Group
38
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PEB 24902 PEF 24902
Technical Description 3.5 Boundary Scan Test Controller
The Quad IEC AFE provides a boundary scan support for a cost effective board testing. It consists of: - Complete boundary scan for 11 signals (pins) according to IEEE Std. 1149.1 specification. - Test access port controller (TAP) - Four dedicated pins (TCK, TMS, TDI, TDO) - One 32-bit IDCODE register - pin TDISS tied to low disables the complete Boundary Scan Test Controller Boundary Scan The following pins are included in the boundary scan: ADDR, CL15, CLOCK, CODE, PDM1, PDM2, PDM3, PDM4, RES, SDR, SDX Depending on the pin functionality one, two or three boundary scan cells are provided. Table 13 Pin Type Input Output I/O Number of Boundary Scan Cells 1 2 3 Usage input output, enable input, output, enable
When the TAP controller is in the appropriate mode data is shifted into or out of the boundary scan via the pins TDI/TDO using the 6.25 MHz clock on pin TCK. The pins are included in the following sequence in the boundary scan: Table 14 Boundary Scan Pin Number Number TDI --> 1 2 3 4 5 6 7 7 8 23 24 25 26 27 Pin Name Type Number of Scan Cells 3 2 1 1 1 1 1 Default value TDI --> 000 10 0 0 0 0 0
05.96
CL15 PDM4 CODE SDX RES CLOCK ADDR
39
I/O O I I I I I
Semiconductor Group
PEB 24902 PEF 24902
Technical Description Table 14 Boundary Scan Pin Number Number TDI --> 8 9 10 11 38 39 40 41 Pin Name Type Number of Scan Cells O O O O 2 2 2 2 Default value TDI --> 00 00 10 01
PDM1 PDM2 PDM3 SDR
TAP Controller The Test Access Port (TAP) controller implements the state machine defined in the JTAG standard IEEE Std. 1149.1. Transitions on the pin TMS cause the TAP controller to perform a state change. Following the standard definition 7 instructions are executable. TAP controller instructions: Table 15 Code 000 001 010 011 100 101 11X Instruction EXTEST INTEST SAMPLE/PRELOAD IDCODE CLAMP HIGHZQ BYPASS Function External testing Internal testing Snap-shot testing Reading ID code Reading outputs Z-State of all boundary scan output pins Bypass operation
EXTEST is used to examine the board interconnections. When the TAP controller is in the state "update DR", all output pins are updated with the falling edge of TCK. When it has entered state "capture DR" the levels of all input pins are latched with the rising edge of TCK. The in/out shifting of the scan vectors is typically done using the instruction SAMPLE/PRELOAD.
Semiconductor Group
40
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PEB 24902 PEF 24902
Technical Description INTEST supports internal chip testing. When the TAP controller is in the state "update DR", all inputs are updated internally with the falling edge of TCK. When it has entered state "capture DR" the levels of all outputs are latched with the rising edge of TCK. The in/out shifting of the scan vectors is typically done using the instruction SAMPLE/PRELOAD. Note: 001 (INTEST) is the default value of the instruction register. SAMPLE/PRELOAD provides a snap-shot of the pin level during normal operation or is used to preload (TDI) / shift out (TDO) the boundary scan with a test vector. Both activities are transparent to the system functionality.
IDCODE Register The 32-bit identification register is serially read out via TDO. It contains the version number (4 bits), the device code (16 bits) and the manufacturer code (11 bits). The LSB is fixed to "1". Version 0001 Device Code 0000 0000 0010 0110 Manufacturer Code 0000 1000 001 1 Output --> TDO
Note: Note:In the state "test logic reset" the code "0011" is loaded into the instruction code register. BYPASS, a bit entering TDI is shifted to TDO after one TCK clock cycle, e.g. to skip testing of selected ICs on a printed circuit board. HIGHZQ sets all pins included to the boundary scan path into a high impedance state. In this state, an in-circuit test system may drive signals onto these pins. CLAMP allows the state of the signals included in the boundary scan driven from the PEB 24902 to be determined from the boundary scan register while the bypass register is selected as the serial path between TDI and TDO. These signals will not change while CLAMP is selected.
Semiconductor Group
41
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PEB 24902 PEF 24902
Digital Interface 4 Digital Interface
Unless otherwise specified, the static and dynamic limits apply over a supply voltage range from 4.75 to 5.25 V and over the temperature range as specified in section 7.2. 4.1 Static Requirements
Table 16 Static Characteristics Parameter High level input voltage Low level input voltage Low level input leakage current High level input leakage current High level output voltage (Pin CL15) High level output voltage (all other outputs) Low level output voltage Input capacitance Symbol min. VIH VIL VIL IIH VOH VOH VOL CIN 4.4 4.0 0.33 10 2.4 - 0.3 - 10 10 Limit Values typ. max. VDD + 0.3 0.8 Unit Test Condition V V A A V V V pF VIN = DGND VIN = DVDD IOH = 5 mA IOH = 1 mA IOL = 1 mA
Semiconductor Group
42
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PEB 24902 PEF 24902
Digital Interface 4.2 Dynamic Requirements
Figure 20 Dynamic Input and Output Requirements at the Digital Interface Table 17 Dynamic Input Characteristics Parameter Signal Symbol t r, t f tcw th tl 20 20 20 5 10 65 Limit Values min. Clock rise / fall time CL15 Clock period Pulse width high / low Data rise / fall time Data setup Data hold CL15 CL15 typ. max. 15 ns ns ns ns ns ns ns Unit
SDX tr, tf XDN1..4 SDX tds XDN1..4 SDX tdh XDN1..4
Note:
There is no value specified for tds or for tdh of the signal at XDN1..4.
Semiconductor Group
43
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PEB 24902 PEF 24902
Digital Interface Table 18 Dynamic Output Characteristics Parameter Signal Symbol tr, tf tcw th tl tD 20 20 20 65 Limit Values min. Clock rise / fall time CL15 Clock period1) Pulse width1) high / low Data delay CL15 CL15 PDM, SDR typ. max. 10 ns ns ns ns ns Unit
1)
This specification is only applicable in case of the usage of the internal PLL/oscillator or if a sinusoidal clock is provided at XIN. It is valid 1ms after power on (free running mode). Boundary Scan Timing
4.3
Figure 21 Boundary Scan Timing
Semiconductor Group
44
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PEB 24902 PEF 24902
Digital Interface
Parameter test clock period test clock period low test clock period high TMS set-up time to TCK TMS hold time from TCK TDI set-up time to TCK TDI hold time from TCK TDO valid delay from TCK
Symbol min. tTCP tTCPL tTCPH tMSS tMSH tDIS tDIH tDOD
Limit Values max. 60 160 70 70 30 30 30 30 -
Unit ns ns ns ns ns ns ns ns
Semiconductor Group
45
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PEB 24902 PEF 24902
Power Supply 5 5.1 Power Supply Supply Voltages VDDd1 to GNDd1 VDDd2 to GNDd2 VDDa1 to GNDa1 VDDa2 to GNDa2 VDDa3 to GNDa3 VDDa4 to GNDa4 5.2 Power Consumption = +5V 0,25V = +5V 0,25V = +5V 0,25V = +5V 0,25V = +5V 0,25V = +5V 0,25V
All measurements with random 2B+D data in active states, 5V (0C - 70C) Table 19 Power Consumption Parameter 98 load at AOUTx/BOUTx (2B1Q mode) 135 load at AOUTx/BOUTx (4B3T mode) 98 load at AOUTx/BOUTx (2B1Q mode) 135 load at AOUTx/BOUTx (4B3T mode) All inputs are tied to VDD or GND Symbol Limit Values min. typ. 820 max. 900 mW all line ports are in power up all line ports are in power up one line port is in power up one line port is in power up all line ports are in power-down Unit Comment
720
800
mW
235
270
mW
210
245
mW
40
60
mW
Semiconductor Group
46
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PEB 24902 PEF 24902
Maximum ratings 6 Maximum ratings
Stresses above those listed in table 20 may cause permanent damage to the device. Exposure to conditions beyond those indicated in section 5.1 of this specification may affect device reliability. This is a stress rating only and functional operation of the device under these conditions or at any other condition beyond those indicated in the operational conditions of this specification is not implied. It is not implied, that more than one of these conditions can be applied simultaneously. Table 20 Maximum ratings Parameter min. positive Supply Voltage Voltage applied at any input Voltage applied at at the line port outputs Voltage between GNDx to any other GNDx Voltage between VDDx to any other VDDx Maximum surge Voltage applied at the line port inputs -0.3 -0.3 Limit Values max. 7.0 VDD + 0.3 max. 7.0 VDD + 0.3 max. 7.0 0.3 0.3 ESD hardness according to MIL-Standard 883d Method 3015.7 V V V V V Unit
6.1
Line Overload Protection
The maximum input current (under over-voltage conditions) is given as a function of the width of a rectangular input current pulse. For the destruction current limits refer to figure 22:
Semiconductor Group
47
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PEB 24902 PEF 24902
Maximum ratings
Figure 22 Maximum Line input current
Semiconductor Group
48
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PEB 24902 PEF 24902
Environmental Requirements 7 7.1 Environmental Requirements Storage and Transportation
The rated (limited capability) storage and transportation temperature range prior to printed board assembly shall be as follows: - 65 to +150C (without supply voltage) 7.2 Operating Ambient
The operating ambient temperature for standard and extended temperature versions shall be within the limits as follows: PEB 24902 0 C to +70 C (standard version) (extended temperature range version) PEF 24902 - 40 C to +85 C 7.3
Thermal Contact Resitance 55 Kelvin/Watt
RTHU (silicon -environment):
Semiconductor Group
49
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PEB 24902 PEF 24902
Package Outlines 8 Package Outlines
Plastic Package, P-MQFP-64 (Plastic Metric Quad Flat Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 50
Dimensions in mm 05.96

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